1. Field of the Invention
The present invention relates to programmable logic devices (PLD's) of a type in which an internal memory of fuse or anti-fuse links is programable via program/verify f(P/V) circuitry to achieve a desired pattern of "open" and "closed" link states which are verifiable via the P/V circuitry.
2. Description of the Related Art
Programmable logic devices (PLD's) include a family of integrated circuits (IC's) with an internal memory array of links of a fuse or an anti-fuse type. A memory array of links of the fuse type has all link states originally "closed" while an array of links of the anti-fuse type has all link states originally "open". The array is programmed in response to high power programming pulses to contain a desired pattern of "open" and "closed" link states in order to customize the PLD's functionality. As a result of the programing, specific links are intended to be brought irreversibly and completely to a state opposite their original state.
While ideally "closed" links should have a zero resistance and "open" links an infinite resistance, this is not achievable in practice. Because zero resistance materials are not available at the operating temperatures of integrated circuits, typically the resistance of a "closed" or intact link may range up to 100.OMEGA. while a distribution of resistance of an "open" link may range from 100 M.OMEGA. down to below 100.OMEGA..
Through proper design and testing methodologies, integrated circuits with link resistance values that would adversely affect functionality can be rejected. Current testing philosophies include a verification during which the links are sequentially selected and the resistance of each selected link is compared with a single reference resistance value, for example 500 K.OMEGA., to classify the link resistance among two resistance zones divided by the reference value, i.e. one resistance zone corresponding to a "closed" or "intact" state and the other resistance zone corresponding to an "open" state. If the resistance of a link is greater than the reference resistance value, the link is considered in the "open" state, otherwise the link is considered in the "closed" state.
Links whose resistance approach the ideally "closed" value of zero or the ideally "open" value of infinity pose no problem. However, as link resistance approaches the reference resistance value, functional and AC failures, which are not usually tested for during or after programing, may result. Functional and AC testing, beyond the usual room temperature functional test, sufficient to identify these possible failures would be unduly costly.